10 G bit TCP Offload Engine + PCIe/DMA SOC IP
INT 20012 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low Latency and Very High Perfor…
10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
INT 20011 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance…
10G TCP Offload Engine+MAC+Host_IF Ultra-Low Latency (SXTOE)
INT 20011 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance…
10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe)
INT 10012 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low Latency and Very High Perfor…
10G TCP+UDP Offload+EMAC+PCIe+Host IF Ultra-Low Latency (SXTOE+UOE+PCIe)
INT 25012 is the only SOC IP Core that implements a full 10G bit TCP and UDP Stack in Handcrafted, Ultra-High Performance, , Flex…
The TCPIP-1G/10G core implements a TCP/IP Hardware Protocol Stack.
TCP/IP Offload Engine - 10G/ 25G/40G/100Gbit/s TCP/IP
Fast, reliable connectivity in any FPGA using a minimum of FPGA resources The TCP/IP (Transmission Control Protocol/ Internet Pro…
1G TCP Offload Engine TOE Very Low Latency (TOE)
INT 1011 is flexible that is customizable for layer-3, layer-4, layer-5 network infrastructure and network security systems appli…
TCP/UDP/IP Network Protocol Accelerator Platform
Accelerate Network Protocols with FPGA TCP/UDP/IP Stack The German Fraunhofer Heinrich-Hertz-Institute (HHI) has partnered with M…
Ultra Low Latency 10G TCP Endpoint
The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
200G / 100G / 40G / 25G / 10G / 1G TCP Offloading Engine
The TCP Offloading Engine IP core (TOE200G/100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU.
Simulation VIP for Ethernet TSN
Mature and capable compliance verification solution.The Cadence® Verification IP (VIP) for Ethernet Time-Sensitive Networks (TSN)…