12-bit ADC on Samsung 8nm LN08LPP
The sf_adc0802x_ln08lpp_306011 is a 1.8V/0.75V dual supply-voltage 16-ch 12-bit analog-to-digital converter (ADC) that supports c…
16b 80Msps DAC with 10KHz BW in samsung 8nm
DA16SD10K08NM is 16b, voltage output, Delta Sigma Digital to analog converter (DAC), clocked at 80Mhz and output bandwidth of 10K…
12b, 2Gsps, Self-Calibrating Current Steering IQDAC in samsung 8nm for 5G & WIFI6
DAIQ12CS2G08NLL is high performance 12b current steering IQDAC that supports data rate up-to 2Gsps.
Dual channel 12-bit, 2GS/s ADC for 5G & WIFI6 in Samsung 8nm
ADIQ12B1G08NLL is a Dual channel 12-bit analog-to-digital converter (ADC) that operates up to 2GS/s.
14b, 4Gsps, Self-Calibrating Current Steering IQ DAC for 5G & WIFI6 in samsung 8nm
DAIQ14CS4G08NLL is high performance 14b current steering IQDAC that supports data rate up-to 4Gsps.
12b, 1Gsps, Self-Calibrating Current Steering IQDAC in samsung 8nm for 5G & WIFI6
DAIQ12CS1G08NLL is high performance 12b current steering IQDAC that supports data rate up-to 1Gsps.
Dual channel 12-bit, 1GS/s ADC in Samsung 8nm for 5G & WIFI6
ADIQ12B1G08NLL is a Dual channel 12-bit analog-to-digital converter (ADC) that operates up to 1GS/s.
Integer PLL on Samsung 8nm LN08LPP
PLLF0816X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Frac-N PLL on Samsung 8nm LN08LPP
PLLF0842X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Temperature Sensor, +/-3C Accuracy without Trimming - Samsung 8nm
Temperature Sensor, +/-3C Accuracy without Trimming - Samsung 8nm
LDO, 1.8V to 0.75V, 100mA Output Capability - Samsung 8nm
LDO, 1.8V to 0.75V, 100mA Output Capability - Samsung 8nm
MIPI D-PHY v1.2 TX 4 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
MIPI D-PHY v1.2 RX 2 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
HDMI 2.0 RX PHY in Samsung (8nm)
The Synopsys HDMI Receiver (RX) IP solutions are compliant with the High- Definition Multimedia Interface (HDMI) 2.0 and 1.4 spec…
LPDDR4 multiPHY V2 in Samsung (8nm) for Automotive
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-o…
50mA Capless High PSRR Regulator LDO Regulator for RF and Analog Applications in Samsung 8nm
DO8NMFF50M is a linear regulator capable of supplying 50mA of regulated output current with programmable output voltages.
The ODT- UCIE-UNI-RX-16GXX-S8 is a low power D2D receiver IP in Samsung 8nm process.
Dual channel 12-bit, 4GS/s ADC IP for 5G in 8nm process
ADIQ12B4G08NLL is a Dual channel 12-bit analog-to-digital converter (ADC) that operates up to 4.0 GS/s.
32G PHY in Samsung (10nm, 8nm, 4nm, 5nm, SF2)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
DDR5/4 PHY in Samsung (10nm, 8nm, 7nm)
The Synopsys DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications req…