PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP
PCI Express Gen 2 Endpoint Controller.
- PCI Express
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP
PCI Express Gen 2 Endpoint Controller.
Memory Controller IP, Memory Stick controller, Soft IP
Memory Stick host controller with AHB Bus.
AHB system Peripheral IP, SRAM/ROM Controller, Soft IP
Embedded synchronous Single Port SRAM/ROM memory controller with up to two AHB slave ports.
AHB system Peripheral IP, External Bus controller, Soft IP
External Bus Interface Controller.
Specialty Analog ESD IO IP, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process 3.3V Analog ESD IO Cell Library.
Specialty OSC IO IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process 1.8V device high frequency crystal osc IO Library.
Specialty Analog ESD IO IP, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process 3.3V Analog ESD IO Cell Library.
Specialty OSC IO IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process 1.8V device low frequency crystal osc IO Library.
Specialty OSC IO IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process 1.8V device high frequency crystal osc IO Library.
Specialty Analog ESD IO IP, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process 1.8V Analog ESD io Cell Library.
General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process mini IO (blown up version of 0.18u Mini-IO).
General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.162um G2 process
UMC 0.162um GII Logic process true 3.3V standard BOAC IO Cell Library (0.18um shrink process).
General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.162um G2 process
UMC 0.162um GII Logic process True 1.8V IO cells.
DDR2/3 Combo SDRAM Controller.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.162um G2 process
UMC 0.162um GII Logic process high density Core Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process Mini-Library.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process Generic Core Cell Library.
Voltage Detector IP, 4 Levels, UMC 0.153um G2 process
4-level detector for USB-OTG, VCCA=3.3V, Ivcca=125uA, UMC 0.153um 1.8V/3.3V GII Logic process.
Linear Regulator IP, Output: 1.8V/150mA, UMC 0.162um Logic process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.162um Logic process.
Linear Regulator IP, Output: 1.8V/150mA, UMC 0.153um MS process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.153um Mixed-Mode/Logic process.