Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.3um HV process
UMC 0.3um HV process Core Cell Library.
- Standard Cell Libraries
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.3um HV process
UMC 0.3um HV process Core Cell Library.
IP
Voltage Detector IP, 4 Levels, HJTC 0.18um eFlash/G2 process
4-level detector for USB applications, input 3.3V, Ivcca=115uA, HJTC 0.18um embedded flash (P-channel cell) process.
USB 2.0 Device PHY IP, Non-Crystal mode support, HJTC 0.11um pFlash/LL process
USB2.0 PHY, crystal-less, HJ 0.11um pflash LL process.
USB 1.1.OTG PHY IP, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process, USB 1.1 OTG.
Standard Cell (MiniLib) Library IP, 7 tracks, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process Mini-Library.
Standard Cell (Generic) Library IP, RTC Cell, HJTC 0.18um eFlash/G2 process
HJ 0.18um eFlash process RTC Standard Cell Library.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.162um eFlash/LL process
UMC 0.162um eFlash/LL 9-Track Generic Core Cell Library.
Specialty OSC IO IP, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process true 3.3V Xtal IO Cell Library.
Specialty OSC IO IP, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process true 1.8V Xtal IO Cell Library.
RC Oscillator IP, Input: 1.62V - 1.98V, Output: 50MHz, HJTC 0.18um eFlash/G2 process
Internal-RC, frequency 50MHz.
RC Oscillator IP, Input: 1.62V - 1.98V, Output: 40MHz, HJTC 0.18um eFlash/G2 process
Internal-RC, frequency 40MHz.
RC Oscillator IP, Input: 1.62V - 1.98V, Output: 100KHz, HJTC 0.18um eFlash/G2 process
Internal-RC, frequency 100KHz.
Power Switch IP, 2 inputs, HJTC 0.18um eFlash/G2 process
2 Input Power Switch, HJTC 0.18um eFlash process.
Power on Reset IP, Input: 2.5V/3.3V, HJTC 0.18um eFlash/G2 process
Vrr=2V Vfr=1.95V, input VCCK=1.8V VCC3IO=3.3V, 3.3V Power On Reset, special request by Hisilicon, HJTC 0.18um 2P6M eFlash process.
Power on Reset IP, Input: 1.8V, Output: 1.8432MHz, HJTC 0.18um eFlash/G2 process
Vrr=1.4V, Vfr=1.15V, 1.8V Power on Reset, HJTC 0.18um eFlash 1.8V/3.3V/5V process.
Power on Reset IP, Input: 1.8V, HJTC 0.18um eFlash/G2 process
Vrr=1.35V, Vfr=1.25V, 1.8V Power on Reset, HJTC 0.18um eFlash 1.8V/3.3V/5V process.
PLL (Frequency Synthesizer) IP, Input: 10MHz, Output: 40MHz - 60MHz, HJTC 0.18um eFlash/G2 process
Input 10MHz, output 40M-60MHz, frequency synthesizable PLL, HJTC 0.18um eFlash process.
Input 10M-200MHz, output 20M-300MHz, frequency synthesizable PLL, HJTC 0.18 eFlash process.
One Port Register File Compiler IP, HJTC 0.18um pFlash process
HJTC 0.18um pFlash process synchronous Single Port Register File memory compiler.