IP
- MIPI D-PHY
- TSMC
- 28nm
- Pre-Silicon
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IP
SATA 3 Host Controller on Xilinx Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 F…
CSMC 0.13um LP process 1.2v/3.3v Generic IO library
USB 1.1 PHY IP, UMC 0.5um Logic process
USB 1.1 PHY, UMC 0.5um Logic process 3.3V 1P3M.
General Purpose IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 5V low voltage IO Cell Library.
Specialty PCI IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 3.3V Oscillator IO cells.
General Purpose IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 3.3V low voltage IO Cell Library.
General Purpose IO IP, 5V tolerance, UMC 0.5um Logic process
UMC 0.5um Logic process 5V tolerance low voltage IO Cell Library.
Specialty PCI IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 5.0V PCI IO cells.
Specialty PCI IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 5.0V Oscillator IO cells.
General Purpose IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 5V standard IO Cell Library.
Specialty PCI IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 3.3V PCI IO cells.
General Purpose IO IP, UMC 0.5um Logic process
UMC 0.5um Logic process true 3.3V standard IO Cell Library.
Power on Reset IP, Input: 3.3V, UMC 0.5um process
Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, L type IO, Power On Reset, UMC 0.5um Logic process low voltage.
Power on Reset IP, Input: 3.3V, UMC 0.5um process
Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process.
Power on Reset IP, Input: 5V, UMC 0.5um process
Vrr=3.4V Vfr=3.0V, VCC=5V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process.
Voltage Detector IP, Vdet: 3.3V, UMC 0.5um process
5V/3.3V detector VDT, UMC 0.5um Logic process.
Standard Cell (Generic) Library IP, UMC 0.5um process
UMC 0.5um Logic process low voltage Core Cell Library.
Standard Cell (Generic) Library IP, UMC 0.5um process
UMC 0.5um Logic process standard Core Cell Library.
PLL IP, Input: 20MHz - 24MHz, Output: 20MHz - 100MHz, UMC 0.5um process
Input 20M-24MHz, output 20M-100MHz, frequency synthesizable PLL, 0.5um Logic process.