UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.
- SRAM
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UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.
UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)
Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]
Fujitsu 90nm LL-UHS process MPCA M345 core cell library
Fujitsu 90nm LL-UHS process MPCA M345 core cell library
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process
5V to 3.3V/1.8V with 80mA/40mA driving capability, Linear Regulator; UMC 0.162um GII process.
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process
Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process
Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS pro…
8V ~ 25V HV driver, UMC 0.35um 3.3V/5V/40V CDMOS logic process
8V ~ 25V HV driver, UMC 0.35um 3.3V/5V/40V CDMOS logic process
5V to 4.2V battery charger with 3.3V device ; UMC 0.153um Logic/Mixed-Mode Process
5V to 4.2V battery charger with 3.3V device ; UMC 0.153um Logic/Mixed-Mode Process
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process
24bit 96KHz A/D converter, 1.8V 3-channel Sigma-Delta Audio ADC; HJTC 0.18um eFlash process
24bit 96KHz A/D converter, 1.8V 3-channel Sigma-Delta Audio ADC; HJTC 0.18um eFlash process
1.8V 10bit 80MSPS Dual-Channel Pipelined ADC; UMC 0.153um Logic Process_x005F_x000D_
1.8V 10bit 80MSPS Dual-Channel Pipelined ADC; UMC 0.153um Logic Process
1.8V 10bit 80MSPS Pipelined ADC; UMC 0.153um Logic Process
1.8V 10bit 80MSPS Pipelined ADC; UMC 0.153um Logic Process
Analog part of 600Mbps to 4Gbps 4-lane V-By-One receiver with embedded CDR circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.
VeriSilicon HHG 0.11um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for HHGrace Semiconductor Manufacturi…
VeriSilicon HHG 0.11um Low-Power(LP) Process Synchronous Memory Compiler optimized for HHGrace Semiconductor Manufacturing Corpor…
HLMC 55nm LP Multiple Power Supply IO library
Multiple power supply IO library for Huali55nm low power 1.2v/2.5v process