LVDS Rx IO IP, UMC 0.18um G2 process
0.13um LVDS RX IO PAD, UMC 0.13um HS/HVT-FSG process.
- UMC
- 180nm
- G
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
LVDS Rx IO IP, UMC 0.18um G2 process
0.13um LVDS RX IO PAD, UMC 0.13um HS/HVT-FSG process.
Voltage Detector IP, 4 Levels, UMC 0.13um LL/FSG process
4-level voltage detector, input 1.2V, Ivcca=65uA, UMC 0.13um LL-LVT(FSG) process.
Linear Regulator IP, Output: 3.3V/100mA, UMC 0.13um HS/FSG process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.13um HS/FSG Logic process.
Linear Regulator IP, Output: 3.3V/50mA, UMC 0.13um HS/FSG process
3.3V with 50mA driving capability, Istb=70uA Linear Regulator, UMC 0.13um HS/FSG Logic process.
PLL (De-Skew) IP, Input: 15MHz - 110MHz, Output: 15MHz - 110MHz, UMC 0.13um HS/FSG process
Input 15M-110MHz, output 15M-110MHz, De-skew PLL with 0.9V~1.32V power supply range, UMC 0.13um HS/FSG Logic process.
PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process
high speed clock generator using UMC 0.13um 1.2V HS process.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Input 10M-200MHz, output 25M-400MHz, frequency synthesizable PLL, UMC 0.13um SP/FSG Logic process.
Ring Oscillator IP, Output: 12KHz, UMC 0.13um HS/FSG process
Self-contained ring oscillator, frequency 12KHz.
RC Oscillator IP, Output: 40MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 40MHz.
RC Oscillator IP, Output: 15MHz - 50MHz, UMC 0.13um HS/FSG process
15M~50MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.
RC Oscillator IP, Output: 4MHz - 15MHz, UMC 0.13um HS/FSG process
4M~15MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Input 20M-200MHz, output 50M-100MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
8 bits 160MS/s pipeline ADC - 0.25um
8 bits 160MS/s pipeline ADC
Advanced Encryption Standard (AES-128) core with AMBA AHB interface
The GRAES core implements the AES-128 symmetric encryption algorithm for high-throughput applications.
8051 Microcontroller
64-bit PCI-X Master/Target