One Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Single Port Register File SRAM memory compiler.
- UMC
- 90nm
- LL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
One Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Single Port Register File SRAM memory compiler.
ROM Compiler IP, UMC 90nm LL process
UMC 90nm Logic process low leakage synchronous Contact VIA1 memory compiler.
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um HV process
UMC 0.18um high voltage 1.8V process synchronous high density Single Port SRAM memory compiler.
ROM Compiler IP, UMC 0.18um LL process
UMC 0.18um Logic low leakage process synchronous Diffusion ROM complier.
Single Port SRAM Compiler IP, UMC 0.15um SP process
UMC 0.15um SP Logic process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.13um CIS process
UMC 0.13um CMOS Image Sensor process synchronous high density Single Port SRAM memory compiler.
Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um LL/FSG process
UMC 0.11um LL Logic process Standard Core Cell Library.
Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG process Generic Core Cell Library.
Standard Cell (Generic) Library IP, 8 tracks, UMC 0.11um SP/FSG process
UMC 0.11um SP Logic process Standard Core Cell Library.
Standard Cell (Generic) Library IP, 10-track, LVT, UMC 90nm SP process
UMC 90nm Low-K SP-LVT Standard Core Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process
UMC 0.18um Logic low leakage process standard Cell Library (mini Library ).
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.13um CIS process
UMC 0.13um CMOS Image Sensor process standard Core Cell Library.
D/A Converter IP, 10 bits, 75MHz, UMC 65nm LL process
3-channel digital-to-Analog converter (Digital-to-Analog converter) with 10-Bit resolution for video application.
D/A Converter IP, 10 bits, 165Msps, UMC 90nm LL process
10-Bit 165MSPS current steering 3-ch Digital-to-Analog converter, UMC 90nm LL Logic(HVT) Low-K process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 36MHz, Output: 500MHz - 1GHz, UMC 90nm SP process
Input 20M-36MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Logic Low-K process.
USB 1.1.OTG PHY IP, OTG, UMC 0.25um Logic process
USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.25um Logic process.
D/A Converter IP, 16 bits, 96Ksps, UMC 0.25um Logic process
16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.25um Logic process.
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0.
SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process
1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA, UMC 0.18um GII Logic process.
Audio ADDA IP, 6 bits, 4MHz, UMC 0.18um G2 process
2-channel 4MHz 6-Bit ADC & 8-Bit DAC, UMC 0.18um GII Logic process.