Input 5M-200MHz, output 12.5M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.11um CMOS Image Sensor process.
- UMC
- 110nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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Input 5M-200MHz, output 12.5M-300MHz, frequency synthesizable PLL with power/ground pad, UMC 0.11um CMOS Image Sensor process.
Input 5M-200MHz, output 12.5M-300MHz, frequency synthesizable PLL, UMC 0.11um CMOS Image Sensor process.
PLL IP, Input: 32.768KHz, Output: 12MHz - 48MHz, UMC 0.11um HS/FSG process
Input 32.768KHz, output 12M-48MHz, PLL, UMC 0.11um HS/Copper Logic process.
RC Oscillator IP, Output: 50MHz, UMC 90nm SP process
Internal-RC, trimmable fixed frequency 50MHz.
Ring Oscillator IP, Output: 12KHz, UMC 90nm Logic process
12KHz Ring OSC.
RC Oscillator IP, Output: 12KHz, UMC 65nm SP process
Internal-RC, trimmable fixed frequency 12KHz.
RC Oscillator IP, Output: 50MHz, UMC 0.18um G2 process
Internal-RC, frequency 50MHz.
RC Oscillator IP, Output: 25MHz / 33MHz, UMC 0.18um eFlash/G2 process
UMC 0.18um eFlash process, Internal-RC, trimmable frequency selected 25MHz/33MHz, VCCA=1.2V~1.8V, VBG=0.615.
RC Oscillator IP, Output: 20MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency 20MHz, VCCA=1.6V~2.0V VBG=0.615V, UMC 0.18um GII Logic process.
RC Oscillator IP, Output: 50MHz / 70MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency selected 50MHz/70MHz.
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process.
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process.
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller u…
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller…
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Enhance…
Band Gap IP, Input: 1.08V - 1.32V, VBG=0.6V, UMC 90nm LL process
Input 1.08V-1.32V, VBG=0.6V, Band Gap, LL process, UMC 90 nm LL Logic/RVT Low-K process.
Band Gap IP, Input: 0.9V - 1.1V, VBG=0.5V, UMC 90nm SP process
Input 0.9V-1.1V, VBG=0.5V, Band Gap, UMC 90nm SP/RVT Logic Low-K process.