10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process
10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.
- UMC
- 110nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process
10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 65nm LP process
UMC 65nm LP/RVT Low-K Logic process UHS (Ultra high speed) Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 65nm SP process
UMC 65nm SP/HVT Low-K Logic process high speed Cell Library.
Standard Cell (Ultra High Speed) Library IP, RVT, 12 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Low-K process high speed Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm LL process
UMC 65nm LL/RVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 65nm LL process
UMC 65nm LL-HVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 65nm SP process
UMC 65nm SP/RVT process Core Cell Library mini Library.
Standard Cell (MiniLib) Library IP, RVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Mini-Library Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 8 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K process Mini-Library Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process
UMC 0.13um LL FSG Logic process Enhanced Mini-Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um HS/FSG process
UMC 0.13um HS process Generic Core Cell Library (enhanced Mini-Library).
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG process enhanced Mini-Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG process high density Core Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Enhanced Mini-Library Standard Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um LL/FSG process
UMC 0.11um LL/FSG Logic process high density Generic Core Cell Library.
Standard Cell (ECO) Library IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process Metal1 Start ECO Core Cell Library (for FSR0H_M).
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process high density Core Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.11um SP/FSG process
UMC 0.11um SP/FSG process mini-lib Core Cell Library.
Standard Cell (MiniLib) Library IP, UMC 0.11um HS/AE process
UMC 0.11um AL/HS Logic process Mini-Library standard Cell Library.
Standard Cell (MiniLib) Library IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AL Logic process high density Cell Library.