LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process
2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process.
- UMC
- 130nm
- SP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process
2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process.
LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process
2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process.
LVDS Rx IO IP, UMC 0.18um Logic process
LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process.
LVDS Rx IO IP, 500Mbps, UMC 90nm LL process
Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process.
LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process
2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process.
LVDS Receiver IP, UMC 90nm SP process
DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process.
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process
2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process.
LVDS Tx IO IP, UMC 90nm SP process
LVDS TX Pad, UMC 0.35um Logic process.
LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process
8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process.
LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process
DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process.
Specialty Analog ESD IO IP, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process with 2.5V device Analog esd IO group.
Specialty Analog ESD IO IP, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process 1.2V Analogesd set.
Specialty Analog ESD IO IP, UMC 90nm LL process
UMC 90nm 1.2V LL/RVT Low-K process Analog esd IO group.
Specialty Analog ESD IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Logic process true 2.5V Analog ESD IO group cell.
Specialty Analog ESD IO IP, UMC 90nm SP process
UMC 90nm SP process 2.5V Analog ESD IO set ( using 2.5V gate oxide).
Specialty OSC IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Low-K Logic process True 3.3V Low frequency OSC IO Cell Library.
Specialty Analog ESD IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process 1.0V AnalogESD set.
Specialty Analog ESD IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process 1.0V Analog esd IO group.
Specialty PCI IO IP, UMC 65nm SP process
UMC 65nm SP/RVT Low-K Logic process 2.5VOD3.3V PCI-X IO Cell Library.
Specialty Analog ESD IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process 3.3V Analog ESD IO Set.