Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 12-Track ECO_M1 Core Cell Library (C38).
- UMC
- 28nm
- HLP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 12-Track ECO_M1 Core Cell Library (C38).
Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track ECO_M1 Cell Library (C35).
Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic process 12-Track ECO_M1 Core Cell Library (C38).
Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/LVT process 12-Track ECO_M1 Core Cell Library (C35).
Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic process 12-Track ECO_M1 Core Cell Library (C38).
Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/HVT process 12-Track ECO_M1 Cell Library (C35).
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic process 9-Track ECO_M1 Core Cell Library (C38).
Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track ECO_M1 Cell Library (C35).
Standard Cell (ECO) Library IP, UMC 0.13um eHV process
UMC 0.13um High-Voltage process ECO Cell Library with metal-1 start.
Standard Cell (ECO) Library IP, UMC 0.11um SP/FSG process
UMC 0.11um SP/FSG process mini-lib ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, 6 tracks, UMC 0.11um eFlash process
UMC 0.11um eFlash/EE2PROM AL process ECO_M1 Mini-Library+ (6-Track) Library.
Specialty SSTL IO IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process 2.5V/3.3V SSTL2-Class II/LVTTL combo IO with POC (Pad On Circuit).
Specialty SSTL IO IP, BOAC (Bonding Over Active Circuit), UMC 90nm SP process
UMC 90nm SP/ Low-K Logic process SSTL2 (ClassI) BOAC IO Cells.
Specialty SSTL IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG SSTL2 (class 1) IO for BOAC.
Specialty PCI IO IP, UMC 90nm SP process
UMC 90nm Low-K SP process true 3.3V PCI-X IO cells Library for Intellon.
Specialty OSC IO IP, 1MHz to 66MHz, UMC 90nm SP process
UMC 90nm SP/RVT process 2.5V high frequency OSC Pad.
Specialty OSC IO IP, UMC 90nm SP process
UMC 90nm SP/RVT process 2.5V low frequency OSC Pad.