Standard Cell (ECO) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Mini-Library Metal1 Start ECO Core Cell Library.
- UMC
- 55nm
- SP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Cell (ECO) Library IP, RVT, UMC 55nm SP process
UMC 55nm SP/RVT Low-K Logic process Mini-Library Metal1 Start ECO Core Cell Library.
Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 12-Track ECO Core Cell Library.
Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 12-Track ECO Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track ECO Core Cell Library.
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 7-Track ECO Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 7-Track ECO Cell Library.
Standard Cell (ECO) Library IP, RVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 8-Track ECO Core Cell Library.
Standard Cell (ECO) Library IP, LVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 8-Track ECO Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 8-Track ECO Core Cell Library.
Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 7-Track ECO_M1 Cell Library.
Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process high performance 12-Track Metal1 Start ECO Core Cell Library.
Standard Cell (ECO) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed ECO_M1 Cell Library (C40).
Standard Cell (ECO) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 12-Track high speed Generic ECO_M1 Core Cell Library.
Standard Cell (ECO) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 12-Track high speed ECO_M1 Cell Library (C40).
Standard Cell (ECO) Library IP, LVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 7-Track ECO_M1 Cell Library.
Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process 7-Track ECO_M1 Cell Library.
Standard Cell (ECO) Library IP, RVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (ECO_M1 Core).
Standard Cell (ECO) Library IP, LVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (ECO_M1 Generic Core).
Standard Cell (ECO) Library IP, HVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (ECO_M1 Core).