IP
- SMIC
- 40nm
- In Production
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IP
32.768KHz Low-Power Oscillator IO
IP
2Kbit Efuse with parallel input and parallel output
Program Voltage:2.5V, Program Temperature:10~40 degrees, 2Kbit Efuse with parallel input and parallel output
256bit Efuse with parallel input and parallel output
Program Voltage:2.5V, Program Temperature:10~40 degrees, 256bit Efuse with parallel input and parallel output
1Kbit Efuse with parallel input and parallel output
Program Voltage:2.5V, Program Temperature:10~40 degrees, 1Kbit Efuse with parallel input and parallel output
1.1V, Max frequency 1.5GHz PLL
1.1V, Max frequency 1.5GHz
1.1/3.3V 10bit 54M 1 channel DAC
1.1/3.3V 10bit 54M 1channel
1.1/3.3V 10bit 2MSPS 8 channel ADC
1.1/3.3V 10bit 2MSPS 8channel
1.1/3.3V 10bit 200KSPS 8 channel ADC
1.1/3.3V 10bit 200KSPS 8channel
1.1/3.3V 10bit 1MSPS 8 channel ADC
1.1/3.3V 10bit 1MSPS 8channel
IPSEC (RFC 4303) 1Gbit IP Core
The IPSEC core is a high performance pipelined implementation of the Encapsulating Security Protocol mode of IPSEC (RFC4303) with…
This 3GPP LTE IP (compliant to release 9) eNodeB PHY Baseband and MAC-PHY API.
PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
Metal Programmable IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process True 1.8V Metal-programmable IO (MPIO) Cell Library.
10/100 Ethernet PHY IP, UMC 90nm SP process
10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process
UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process Low Power standard Cell Library.
Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process
UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library.
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process
UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version).
Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process
UMC 65nm SP/HVT process POWERSLASH Cell Library.