Linear Regulator IP, UMC 0.13um HS/FSG process
USB 2.0 Two Port PHY, UMC 0.13um HS/FSG Logic process.
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Linear Regulator IP, UMC 0.13um HS/FSG process
USB 2.0 Two Port PHY, UMC 0.13um HS/FSG Logic process.
SATA II PHY IP, UMC 0.13um HS/FSG process
3G/1.5G Serial ATA PHY, UMC 0.13um HS/FSG Logic process.
Linear Regulator IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process 3.3V to 1.2V with 100mA driving capability, Linear Regulator with Capacitor-Free.
SATA II PHY IP, UMC 0.11um HS/FSG process
3G/1.5G Serial ATA PHY, UMC 0.11um HS/FSG Logic process.
Linear Regulator IP, Output: 3.3V/70mA, UMC 0.25um process
3.3V with 70mA driving capability, Istb=75uA Linear Regulator, 0.25um Logic process.
Linear Regulator IP, Output: 3.3V/250mA, UMC 0.25um process
3.3V with 250mA driving capability, Istb=85uA Linear Regulator, UMC 0.25um Logic process.
Linear Regulator IP, Output: 3.3V/150mA, UMC 0.25um process
3.3V with 150mA driving capability, Istb=75uA Linear Regulator, 0.25um Logic process.
Linear Regulator IP, Input: 4.0V-5.5V, Output: 3.3V / 250mA, 1.8V / 70mA, UMC 0.18um G2 process
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 2.0V-4.0V, Output: 1.8V / 100mA, UMC 0.18um G2 process
3.3V with 100mA driving capability, Istb=100uA Linear Regulator, 0.18um GII Logic process.
5V with 250mA driving capability, Istb=120uA Linear Regulator, UMC 0.18um GII Logic process.
3.3V with 150mA driving capability, Istb=96uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 60mA, UMC 0.18um G2 process
3.3V with 60mA driving capability, Istb=85uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 1.65V-3.6V, Output: 1.8V / 240mA, UMC 0.18um G2 process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process.
General Purpose Multi-Voltage IO IP, With Power-on Control features, UMC 0.11um eFlash process
UMC 0.11um eFlash/EE2PROM Process BOAC Multi-Voltage IO with Power-on Tri-state/Low Function.
General Purpose Multi-Voltage IO IP, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process Multi-Voltage BOAC IO Cell Library (with customized PU/PD function).
General Purpose Multi-Voltage IO IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process Multi-Voltage BOAC IO Cell Library.
General Purpose IO IP, 5V tolerance, UMC 55nm SP process
UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate process 5V Tolerant BOAC IO Cell Library.
General Purpose IO IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process True 3.3V Generic IO Cell Library.
General Purpose IO IP, UMC 28nm HPC process
UMC 28nm Logic and Mixed-Mode Low-K HPC process 1.8V BOAC IO Cell Library.
General Purpose IO IP, UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 1.8V BOAC IO Cell Library.