MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process
MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process
- UMC
- 28nm
- HPC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process
MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process
MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process
MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process
MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process
1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process
1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process
100MHz single-ended to differential clock buffer for UMC 40nm LP.
100MHz single-ended to differential clock buffer for UMC 40nm LP.
LVDS Transmitter 700Mbps; UMC 28nm HPC Process
LVDS Transmitter 700Mbps; UMC 28nm HPC Process
2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout )
2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process.
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip
LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process
LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process
8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process
8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process