UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
- UMC
- 28nm
- HPC
- Pre-Silicon
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
UMC 0.18um GII Logic Process 3.3V core cell library
UMC 0.18um GII Logic Process 3.3V core cell library
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 40nm LP/RVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/RVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library
UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library
UMC 0.13um HS/FSG Logic Process metal2-start programming gate array cell library for FSC0H_J (ECO_M2)
UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library
UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library
UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library
UMC 0.3um HV process, M1-start ECO (engineering change order) core cell library
UMC 0.13um LL/FSG Logic Process miniLib+ M1 ECO cells
UMC 0.13um LL/FSG Logic Process miniLib+ M1 ECO cells
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)
UMC 90nm SP RVT process SSTL18 IO cell library
UMC 90nm SP RVT process SSTL18 IO cell library
UMC 90nm Logic/Mixed Mode SP(RVT) Low-K process;True 3.3V PECL IO Library.
UMC 90nm Logic/Mixed Mode SP(RVT) Low-K process;True 3.3V PECL IO Library.
UMC 0.13um LL process PCI I/O cells.