UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM
- UMC
- 55nm
- ULP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy.
28nm HPM SP-SRAM with Row and 2 Column Repair
28nm HPM SP-SRAM with Row and 2 Column Repair
28nm HPM SP-SRAM with row and 1 column repair
28nm HPM SP-SRAM with row and 1 column repair
UMC 28nm HPM process synchronous LVT preiphery high density single port SRAM memory compiler with Row and 2 Column Repair
28nm HPM SP-SRAM with peri LVT & row & 1 column repair
28nm HPM SP-SRAM with peri LVT & row & 1 column repair
28nm HPM SP-SRAM with peri LVT & 2 column repair
28nm HPM SP-SRAM with peri LVT & 2 column repair
28nm HPM SP-SRAM with peri-LVT 1 column repair
28nm HPM SP-SRAM with peri-LVT 1 column repair
28nm HPM SP-SRAM with 2 column redundancy
28nm HPM SP-SRAM with 2 column redundancy
28nm HPM SP-SRAM with 1 column redundancy
28nm HPM SP-SRAM with 1 column redundancy
UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundan…
UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundan…
UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler
UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT
UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4
UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming
UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35)