GSMC 0.18um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS.
- High-Speed
- Pre-Silicon
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GSMC 0.18um CIS process LVDS Transceiver Pad
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS.
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UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler.
UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler.
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler
UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler.
UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler.
UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler.
UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler.
UMC 55nm Logic process standard synchronous Contact ROM memory compiler.
UMC 55nm Logic process standard synchronous Contact ROM memory compiler.
UMC 55nm Logic process standard synchronous Contact ROM memory compiler.
UMC 55nm Logic process standard synchronous Contact ROM memory compiler.
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler
UMC 28nm HPC Process dual port SRAM with power gating
UMC 28nm HPC Process dual port SRAM with power gating
UMC 28nm HPC process PG Dual Port SRAM with LVT
UMC 28nm HPC process PG Dual Port SRAM with LVT
UMC 28nm HPC process PG-Dual Port SRAM with LVT
UMC 28nm HPC process PG-Dual Port SRAM with LVT
UMC 28nm HPC process Dual Port SRAM with Power gating
UMC 28nm HPC process Dual Port SRAM with Power gating
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT