1.4V~3.6V to 1.2V with 100mA driving capability; Linear Regulator; UMC 90nm LL/RVT LowK LOGIC PROCESS minLib Cell Library
- UMC
- 90nm
- LL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1.4V~3.6V to 1.2V with 100mA driving capability; Linear Regulator; UMC 90nm LL/RVT LowK LOGIC PROCESS minLib Cell Library
3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process
3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 2.5V Regulator with 150mA; UMC 40nm LP/RVT LowK Logic Process
3.3V to 2.5V Regulator with 150mA; UMC 40nm LP/RVT LowK Logic Process
3.3V to 1.8V/150mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process
3.3V to 1.8V/150mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process
3.3v to 2.5v/5mA , REG, Linear Regulator, UMC 55nm LP/RVT Logic Process
3.3v to 2.5v/5mA , REG, Linear Regulator, UMC 55nm LP/RVT Logic Process
2.7V~3.3V to 1.8V with 150mA driving capability; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator using MIFS C40LP Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator using MIFS C40LP Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator, UMC 40nm LP/RVT LowK Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator, UMC 40nm LP/RVT LowK Logic Process
2 Input Power Switch; UMC 55nm LP/RVT LowK Logic Process
2 Input Power Switch; UMC 55nm LP/RVT LowK Logic Process
Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC=1.1V& VCC3V=3.3V, 1.1/3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP Logic Process
Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC=1.2V& VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm uLP/SST Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process
Input VCC=1.2V & VCC3V=3.3V, 1.2/3.3V Power On Reset; UMC 55nm eflash Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process
Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process
1.8V RTC Power-On-Reset, UMC 28nm HPC Process
1.8V RTC Power-On-Reset, UMC 28nm HPC Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset; UMC 55nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process
Input VCC3V=3.3V, 3.3V Power On Reset without Vfr; UMC 55nm LP Logic Process