UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
- UMC
- 55nm
- ULP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery h…
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery h…
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high d…
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high d…
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x000D_
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm eFlash process process ULL ROM Memory Compiler
UMC 55nm eFlash process process ULL ROM Memory Compiler