UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.
- UMC
- 40nm
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UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.
UMC 40nm Low Power Process One Port Register File with 213 cell
UMC 40nm Low Power Process One Port Register File with 213 cell
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral
UMC 40nm Low Power Process One Port Register File wit 213 cell
UMC 40nm Low Power Process One Port Register File wit 213 cell
UMC 28nm HPM ultra high speed register compiler
UMC 28nm HPM ultra high speed register compiler
UMC 28HPM UHS 1PRF
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler
UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 65nm SP/RVT Logic Process MPCA cell library
UMC 90nm LL/RVT MPCA core cell library
UMC 90nm LL/RVT MPCA core cell library
UMC 0.18um Generic process MPCA core cell library
UMC 0.18um Generic process MPCA core cell library
UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)
UMC 28nm HPM/RVT Process 9-track PSK core cells Library(35nm)
UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)
UMC 28nm HPM/LVT Logic Process 9-track PowerSlash cell library (C35)
UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)
UMC 28nm HPM/HVT Logic Process 9-track standard cell Powerslash library (C35)
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias.