DisplayPort heralds a new alternative in video connectivity.
- Displayport
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
DisplayPort heralds a new alternative in video connectivity.
The Bitec HDCP IP Core is for use with the Bitec DP and HDMI IP cores.
40G/50G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral
UMC 28nm HPC Process PG Via ROM Compiler
UMC 28nm HPC Process PG Via ROM Compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm uLP process ULL Via1 ROM compiler
UMC 40nm ultra low power via1 ROM complier
UMC 40nm ultra low power via1 ROM complier
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm EFLASH Process Via ROM Memory complier
UMC 55nm EFLASH Process Via ROM Memory complier
UMC 28HPC process standard synchronous high density TCAM memory compiler
UMC 28HPC process standard synchronous high density TCAM memory compiler
UMC 40nm LP process standard synchronous high density TCAM memory compiler.
UMC 40nm LP process standard synchronous high density TCAM memory compiler.
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral