UMC L55LP 55nm Deskew PLL - 60MHz-300MHz
True Circuits, Inc.
•
HQ:
USA
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 55nm
- LP
Compare 3,564 PLL IP Listing from 105 vendors
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UMC L55LP 55nm Deskew PLL - 120MHz-600MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 55nm
- LP
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UMC L55LP 55nm Deskew PLL - 240MHz-1200MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 55nm
- LP
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UMC L40LP 40nm Deskew PLL - 75MHz-375MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 40nm
- LP
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UMC L40LP 40nm Deskew PLL - 150MHz-750MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 40nm
- LP
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UMC L40LP 40nm Deskew PLL - 300MHz-1500MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 40nm
- LP
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UMC L40G 40nm Deskew PLL - 170MHz-850MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 40nm
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UMC L40G 40nm Deskew PLL - 340MHz-1700MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 40nm
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UMC L40G 40nm Deskew PLL - 680MHz-3400MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- UMC
- 40nm
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TSMC CLN28HPL 28nm Deskew PLL - 110MHz-550MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPL
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TSMC CLN28HPL 28nm Deskew PLL - 220MHz-1100MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPL
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TSMC CLN28HPL 28nm Deskew PLL - 440MHz-2200MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPL
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TSMC CLN28HPM 28nm Deskew PLL - 175MHz-875MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPM
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TSMC CLN28HPM 28nm Deskew PLL - 350MHz-1750MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPM
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TSMC CLN28HPM 28nm Deskew PLL - 700MHz-3500MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 28nm
- HPM
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TSMC CLN20SOC 20nm Deskew PLL - 175MHz-875MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 20nm
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TSMC CLN20SOC 20nm Deskew PLL - 350MHz-1750MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 20nm
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TSMC CLN20SOC 20nm Deskew PLL - 700MHz-3500MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 20nm
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GF L55LPE 55nm Clock Generator PLL - 60MHz-300MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- GlobalFoundries
- 55nm
- LPe
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GF L55LPE 55nm Clock Generator PLL - 120MHz-600MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- GlobalFoundries
- 55nm
- LPe