SMIC 0.18um 12-bit 1M/200K Single-Ended 3.3v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
- 12 Bit
- SMIC
- 180nm
- G
SMIC 0.18um 12-bit 1M/200K Single-Ended 3.3v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
IBM 65nm 12-bit 1M/200K Single/Differential 2.5v Rail to Rail SAR ADC
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
This IP core features a full-hardware sound compressor using the algorithm IMA ADPCM.
SMIC 0.18um 12-Bit 8 Input 1M/200k SAR ADC
The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
4K JPEG 2000 Encoder/JPEG 2000 Decoder
The Ultra High Resolution JPEG 2000 Encoder & Decoder familly of IP cores goes beyond the resolution limit for processed images (…
SMIC 0.13um 1.2v 200MHz Ring Oscillator
The SMIC18_CODEC_01 specifies the design of a high-performance 16-bit stereo Audio CODEC for portable digital audio systems.
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to reach 10-bit resolution.
12-bit 8 Input 1M/200k SAR ADC)
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
12-bit 1M Differential Rail to Rail SAR ADC
The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
SpaceWire link controller with SpaceWire RMAP support and AMBA host interface
The GRSPW2 core implements a SpaceWire link controller with SpaceWire RMAP support and AMBA host interface.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Aliathon’s OTN Framer Core implements OTU, ODU and OPU layer functions and provides an integrated Reed-Solomon FEC codec in a fle…
Audio ADDA IP, 16 bits, 96KHz, UMC 0.18um G2 process
16-Bit 96KHz Sigma-Delta audio Codec, UMC 0.18um GII Logic process.
Image Codec/Encoder/Decoder - ISO/IEC 10918-1 JPEG standard
Image Codec/Encoder/Decoder - ISO/IEC 10918-1 JPEG standard
Hantro VC9800E enables up to 256 streams encoding with high video quality single-core solution, or multi-core solution, supportin…
Image codec/encoder/decoder (Customizable) - ISO/IEC 10918-1 JPEG standard
Supported Standards ISO/IEC 10918-1 JPEG standard Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pi…
SDI Mapper for TICO-RDD35 & TicoXS (JPEGXS) lightweight codecs
Extend 4K or 8K using today's deployed HD-SDI/3G-SDI systems The IPX-SDI-MAP IP-cores enable to efficiently transport TICO RDD35 …
Perceptual Video Quality Optimization IP
Designed for AI-driven video pre-processing, ensuring quality optimization with low latency and real-time performance
ST 2110 enables standards based media transport over IP for providing individual packetization of video, audio and metadata.