IP
- USB 2.0
- SMIC
- 40nm
- LL
- In Production
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IP
VeriSilicon UMC 0.18μm CF I/O
VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II lo…
IP
IP
GP Successive Approximation A/D
IP
2-ch 24-bit 192KSPS Audio DAC; TSMC 40nm LP
IP
10/100 Base-TX Fast Ethernet PHY; TSMC 55nm GP
IP
USB 2.0 OTG PHY IP, OTG, UMC 0.153um Logic process
USB OTG 2.0 PHY, UMC 0.153um Logic process.
Controller IP, SPI Flash controller, Soft IP
Flash Controller with SPI Interface.
AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
L2 cache controller with AXI interface.
AXI system Peripheral IP, Interrupt Controller, Soft IP
Generic Interrupt Controller with AXI interface.
AXI system Peripheral IP, AXI to AXI Bridge, Soft IP
AMBA AXI to AXI Bridge.
AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP
AMBA AXI to AHB Bridge.
AHB system Peripheral IP, Interrupt controller, Soft IP
Interrupt controller with AHB interface.
AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP
AHB to AXI bridge.
DMA controller with AXI interface.
AHB system Peripheral IP, AHB - to - AHB Bridge, Soft IP
AHB to AHB bridge.
Two Port Register File Compiler IP, UMC 0.162um Logic process
UMC 0.162um Logic process synchronous Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.162um G2 process
UMC 0.162um GII Logic process synchronous high density Single Port Register File SRAM memory compiler.