RC Oscillator IP, Output: 40MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 40MHz.
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
RC Oscillator IP, Output: 40MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 40MHz.
RC Oscillator IP, Output: 15MHz - 50MHz, UMC 0.13um HS/FSG process
15M~50MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.
RC Oscillator IP, Output: 4MHz - 15MHz, UMC 0.13um HS/FSG process
4M~15MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Input 20M-200MHz, output 50M-100MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
8 bits 160MS/s pipeline ADC - 0.25um
8 bits 160MS/s pipeline ADC
Advanced Encryption Standard (AES-128) core with AMBA AHB interface
The GRAES core implements the AES-128 symmetric encryption algorithm for high-throughput applications.
8051 Microcontroller
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Specialty PCI IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 3.3V PCI IO cells.
Specialty PECL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process Low Voltage true 3.3V PECL IO cells.
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells.
General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process standard Multi-Voltage IO.
Linear Regulator IP, Output: 3.3V/240mA, UMC 0.18um LL process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
Voltage detector for flash protect, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
VDT for MMC, UMC 0.18um LL Logic process.
Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.18um LL Logic process.