Voltage Detector IP, 4 Levels, UMC 90nm LL process
4-Level Voltage Detector for USB-OTG, UMC 90nm LL Logic/RVT Low-K process and 2.5V overdrive 3.3V device.
- UMC
- 90nm
- LL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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Voltage Detector IP, 4 Levels, UMC 90nm LL process
4-Level Voltage Detector for USB-OTG, UMC 90nm LL Logic/RVT Low-K process and 2.5V overdrive 3.3V device.
Voltage Detector IP, 4 Levels, UMC 90nm SP process
4-Level Voltage Detector for USB-OTG, UMC 90nm Lgic SP/RVT Low-K process and 2.5V overdrive 3.3V device.
Voltage Detector IP, 4 Levels, UMC 65nm SP process
4-Level Voltage Detector for USB-OTG (2.5V overdrive 3.3V device), UMC 65nm SP Logic-HVT Low-K process.
Voltage Detector IP, 4 Levels, UMC 55nm SP process
4-Level Voltage Detector for USB-OTG, UMC 55nm 2.5V overdrive 3.3V device SP/HVT Low-K Logic process.
Voltage Detector IP, VCC: 1.8V, Vdet=1.3V, UMC 0.18um G2 process
Vdet=1.3V Vhys=0.1V, VCCA=1.8V, Ivcca=35uA, UMC 0.18um GII Logic process.
Linear Regulator IP, Output: 1.2V/100mA, UMC 90nm SP process
2.5V to 1.2V with 100mA driving capability, Istb=50uA, Linear Regulator, UMC 90nm SP/RVT Low-K process.
Linear Regulator IP, Output: 1.2V/60mA, UMC 90nm LL process
1.8V to 1.2V with 60mA driving capability, Istb=80uA, Linear Regulator, UMC 90nm LL Logic/RVT Low-K process.
Linear Regulator IP, Output: 1.2V/150mA, UMC 65nm LL process
3.3V to 1.2V with 150mA driving capability, Istb=200uA, Linear Regulator, UMC 65nm LL/RVT Low-K Logic process.
Linear Regulator IP, Output: 2.5V/150mA, UMC 65nm SP process
3.3V to 2.5V with 150mA driving capability, Linear Regulator, UMC 65nm SP/RVT Low-K Logic process.
Linear Regulator IP, Output: 3.3V/120mA, UMC 0.18um G2 process
3.3V with 120mA driving capability, Istb=60uA Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 5.0V, Output: 3.3V/250mA, 1.8V/70mA, UMC 0.18um G2 process
5V to 3.3V/1.8V with 250mA/70 mA driving capability, Istb=80uA, Linear Regulator, UMC 0.18um GII Logic process.
Linear Regulator IP, Input: 4.0-5.5V, Output: 3.3V/250mA, 1.8V/70mA, UMC 0.18um eFlash/G2 process
5V to 3.3V and 1.8V with 250mA and 70mA driving capability, Istb=200uA, Linear Regulator, UMC 0.18um eFlash process.
Linear Regulator IP, Input: 3.3V, Output: 1.8V/150mA, UMC 0.18um eFlash/G2 process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.18um eFlash process.
Linear Regulator IP, Output: 3.3V/200mA, UMC 0.13um HS/FSG process
5V to 3.3V(200mA) & 1.2V(110mA) audio solution regulator, UMC 0.13um HS/FSG Logic process.
Linear Regulator IP, Output: 1.2V/100mA, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process 3.3V to 1.2V with 100mA driving capability, High PSRR linear Regulator.
3.3V to 1.8V high efficiency converter with 200mA driving capability PWM Regulator, UMC 0.13um HS/FSG Logic process.
3.3V to 1.8V high efficiency converter with 150mA driving capability, PWM Regulator, UMC 0.13um LL Logic/FSG process.
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.2V/50mA, UMC 0.13um HS/FSG process
3.3V to 1.2V high efficiency converter with 50mA driving capability, PWM Regulator, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 1.0V/3.3V, UMC 90nm SP process
Vrr=2V Vfr=1.95V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset, special request by ASAL, UMC 90nm SP/RVT Low-K Logic process.
Power on Reset IP, Input: 3.3V, UMC 90nm SP process
Vrr=Vfr=2V, input VCC3IO=3.3V, 3.3V RTC Power On Reset, special request by MTD, UMC 90nm SP/RVT Low-K Logic process.