USB 1.1.OTG PHY IP, UMC 90nm LL process
USB1.1 PHY feature USB 1.1 Type PHY, Technology Type process USB 1.1 On-The-Go PHY, UMC 90nm LL Logic process.
- UCIe 1.1
- UMC
- 90nm
- LL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
USB 1.1.OTG PHY IP, UMC 90nm LL process
USB1.1 PHY feature USB 1.1 Type PHY, Technology Type process USB 1.1 On-The-Go PHY, UMC 90nm LL Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 65nm LL process
USB 1.1 OTG PHY, UMC 65nm LL Logic/RVT Low-K process.
USB 1.1 PHY IP, UMC 65nm SP process
ID Detector for USB OTG Function, UMC 65nm SP/HVT Low-K Logic process.
USB 1.1 PHY IP, UMC 0.18um eFlash/G2 process
USB 1.1 PHY, UMC 0.18um e-flash process.
USB 1.1.OTG PHY IP, OTG, UMC 0.18um eFlash/G2 process
USB 1.1 OTG, UMC 0.18um e-flash process.
USB 1.1.OTG PHY IP, UMC 0.11um HS/FSG process
USB1.1 PHY feature USB 1.1 Type PHY, Technology Type process USB 1.1 On-The-Go PHY, UMC 0.11um HS/Copper Logic process.
SATA II PHY IP, Gen-2, UMC 90nm SP process
Serial ATA I II PHY, UMC 90nm SP/RVT Low-K Logic process.
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Over sampling 1 port 3G/1.5G SATA PHY, UMC 0.13um HS+LL/FSG Logic process.
SATA II PHY IP, Gen-2, UMC 0.11um HS/AE process
3G/1.5G Serial ATA PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.
PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process
4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process.
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process
PCI-Express II PHY, UMC 90nm SP/RVT Low-K process.
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process
PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process.
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process.
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process synchronous high density Two Port Register File SRAM memory compiler.