The VDC-M 1.2 Decoder IP Core fully complies with VESA VDC-M 1.2 (Display Compression).
- VESA DSC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The VDC-M 1.2 Decoder IP Core fully complies with VESA VDC-M 1.2 (Display Compression).
25 to 500 MHz LNA with 0.8 dB NF and 19 dB gain
055TSMC_LNA_02 is an electronic amplifier intended to amplify a very low power signal without significantly degrading its SNR.
500-1750MHz LNA with 1dB NF and 19dB gain
055TSMC_LNA_01 is an electronic amplifier intended to amplify a very low power signal without significantly degrading its SNR.
Wideband LNA with a gain adjustment range from -22 to 20dB
180TSMC_LNA_14 is a IP block which includes a low-noise amplifier (LNA), gain control system and supply voltage controller.
The eSi-POLY1305 core is an easy to use POLY1305 accelerator peripheral that is fully compliant with the RFC7539 IETF standard.
The eSi-CHACHA20 core is an easy to use CHACHA20 stream cipher hardware accelerator that is compliant with the IETF RFC7539 stand…
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
The SM4-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the SM4 algorithm (a block cipher specifi…
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC
The MIPI M-PHY Gear 4 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4…
MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
The MIPI D-PHY Analog RX IP Core completely complies with the D-PHY specification, version 1.2.
We provide configurable USB 2.0 device controller IP Cores.
Hardware root key generation and storage that never leaves the chip PUFrt includes a 1024-bit physical unclonable function (PUF) …
The agileLDO is a linear Low Drop-Out voltage regulator (LDO) providing precision and programmable voltage regulation.
8/10-bit Digital-to-Analog Converter
The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture.
12-bit ultra-low power single-ended SAR ADC
040TSMC_ADC_01 is 12-bit analog to digital converter (ADC) with single-ended input of sample rates up to 1MSPS.
6-bit, 1 GSPS High Performance AFE in 28nm CMOS
The ODT-AFE-6B1G-28HPCPT is a high-performance I/Q ADC and I/Q DAC designed in a 28nm CMOS process.
Radio Clock (DCF77) Master core
NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Radio Clock (DCF77) Slave core
NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DC…
Real Time Clock (RTC) Master core
NetTimeLogic’s RTC Master Clock is a full hardware (FPGA) only implementation of a synchronization core allowing to read and writ…
NMEA Time of Day (ToD) Slave core
NetTimeLogic’s NMEATime Of Day (ToD) Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to …