Vendor: True Circuits, Inc. Category: Single-Protocol PHY

TSMC CLN12FFCP 12nm LPDDR4 PHY - 4266Mbps

The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically a…

TSMC 12nm FFC View all specifications

Overview

The TCI LPDDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is included for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings. Remarkable physical flexibility allows the PHY to adapt to each customer’s die floorplan and package constraints, yet is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY is DFI 5.1 compliant, and when combined with an appropriate LPDDR memory controller, a complete and fully-automatic LPDDR system is realized.

Key features

  • Supports LPDDR4
  • DFI 5.1 compliant
  • Supports x4, x8 and x16 DRAMs
  • Up to 72 bits wide and up to 4 ranks
  • Includes PLL, with frequency multiplication from low frequency reference
  • Per pin architecture automatically corrects skew, increases data eye and eliminates most parallel interface problems
  • Fully automatic training is managed by a light weight special purpose processor
  • Continuous adjustment of read gate and data eye timing
  • Localized and optimized PHY-to-memory controller interface to ease timing closure
  • Full speed read/write BIST with pseudo-random data, mux-scan ATPG and 1149.1 Boundary Scan

Block Diagram

Benefits

  • Automatic Deskew - Skew among pins is automatically corrected; intentional skew can reduce SSO
  • Tuning - State-of-the-art tuning is the key to a high performance DDR system
  • Complete PHY - Completely assembled and validated hard PHY and I/O ring means no assembly is required and performance is guaranteed
  • Compatible - DFI 5.1 compliance and PHY independent training allows for compatibility with a variety of memory controllers
  • Flexibility - Proprietary tools generate and validate a PHY fitted to the customer’s die floorplan and package
  • Timing Closure - Memory controller to PHY timing closure is simplified by a localized synchronous interface
  • Instrumentation - PHY resources can measure data eye and jitter per pin, speeding up board bring-up

What’s Included?

  • GDSII and LVS Spice netlist, behavioral, synthesis and LEF models for hard macros
  • RTL code and SDC constraints for soft logic
  • IBIS and Spice models for RDL, package and PCB simulations
  • Extensive user documentation
  • Integration support to ensure a successful tapeout

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC

Specifications

Identity

Part Number
TCI-TN12FFCP-LPDDR4PHY - 4266Mbps
Vendor
True Circuits, Inc.

Provider

True Circuits, Inc.
HQ: USA
True Circuits develops and markets a broad range of industry leading PLL, DLL and DDR PHY hard and soft macros for ICs for the semiconductor, systems and electronics industries. TCI’s robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world’s leading fabs, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. The True Circuits DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is managed by a light weight special purpose processor for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings. True Circuits DDR PHYs support LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3 in single and multi-protocol versions and are available in a wide variety of TSMC processes. They are configured to each customer’s die floorplan and package constraints, and are delivered and verified as a single unit for easy timing closure with no assembly required. They are DFI 5.1 compliant, and when combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized. True Circuits’ complete family of standardized and silicon-proven clock generator, general purpose, deskew, spread spectrum, IoT and Ultra PLLs and multi-slave and multi-phase DLLs spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low jitter PLL and DLL hard macros are optimized for a wide variety of interface standards, including DDR, HBM, ONFI, PCIE, Ethernet and HDMI. True Circuits also offers synthesizable PLLs and DLLs with timing features, performance and flexibility for a wide range of customer applications. These soft macros include the Precision PLL, micro PLL and micro DLL. True Circuits PLLs and DLLs are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in a wide variety of TSMC, UMC and GlobalFoundries processes. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks. Since 1998, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers’ products with production volumes well into the billions. When only the best will do, go with the timing experts!

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Frequently asked questions about Single-Protocol PHY IP

What is TSMC CLN12FFCP 12nm LPDDR4 PHY - 4266Mbps?

TSMC CLN12FFCP 12nm LPDDR4 PHY - 4266Mbps is a Single-Protocol PHY IP core from True Circuits, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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