SPI/SPANSION FLASH Verification IP

SPI/SPANSION FLASH Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/SPANSION FLASH Verification IP is fully compliant with SPI Block Guide V04.01 of the Motorola's M68HC11 user manual rev 5.0 SPI-Bus Specification and S25FL008A and S25FL512S Specification and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI/SPANSION FLASH Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI/SPANSION FLASH Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Follows SPI/SPANSION FLASH basic specification as defined in S25FL008A and S25FL512S.
• Support Master and Slave Mode
• Supports data width of 8 bit
• Supports bus width 1 bit and 4 bit
• Support baud rate selection
• Supports standard, fast and high speed operations.
• Support internal clock division check.
• Supports flexible erase operation like,
• 4KByte sector erase.
• 8KByte block erase.
• 32KByte block erase.
• 64KByte block erase.
• Support Clock Polarity and Clock Phase selections.
• Support single and burst transfer mode.
• Support on the fly generation of data.
• Supports constraints Randomization.
• Glitch insertion and detection
• Built in functional coverage analysis.
• Supports backdoor initialization of data.
• Status counters for various events on bus.
• Supports single,dual bus width operation
• Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI/SPANSION FLASH.
• SPI/SPANSION FLASH Slave can be configured as standard device or can use FIFO for data passing.
• Master contains rich set of commands for both standard device and FIFO model mode.
• Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
• SPI/SPANSION FLASH Verification IP comes with complete test suite to test every feature of SPI/SPANSION FLASH specification.

• Faster testbench development and more complete verification of SPI/SPANSION FLASH designs.
• Easy to use command interface simplifies testbench control and configuration of slave and master.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the SPI/SPANSION FLASH testcases.
• Examples showing how to connect various components, and usage of Master, Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.