Overview
This is a versatile system-on-chip device designed for automotive, security and a multitude of other camera applications. From video and audio input through HDR image signal processing, lens distortion correction, graphics overlay, video compression, video analytics acceleration, CPU, operating and non-volatile memory, media access controller, to video and audio outputs and communication interfaces, it comprises all elements to support compact, low bill-of-material and low energy-consumption camera applications. No external memory chips such as DRAM or Flash are required for its operation, predictive H.264 video encoding inclusive. Resulting ready-for-display video can be output as-is over the parallel or serial video output port, or real-time compressed for streaming out through one of: RGMII/GMII, SDIO or SPI interfaces. An audio signal can be input through either an I2S or a PDM input, processed by the CPU and inserted into the output data stream. A return audio channel is also supported, outputting the audio on an I2S output. Precise Time Protocol (PTP) support and other provisions on the die allow precise instant-of-exposure synchronization of cameras in a multi-camera system, independent of cable lengths. A cryptographic and hash unit permits protection of customer intellectual property embedded in their software. Flash content can be updated via communication interfaces, thus allowing non-intrusive customer firmware updates. A debug access port (DAP) helps users in their software
Learn more about ISP Image Signal Processor IP core
Intigia has developed AceleradorSNN, a third-generation artificial intelligence cognitive system. This architecture integrates a Neuromorphic Processing Unit (NPU) based on Spiking Neural Networks (SNNs) to process asynchronous data from Dynamic Vision Sensors (DVS), alongside a dynamically reconfigurable Cognitive Image Signal Processor (ISP) for RGB cameras.
Jiang Wang, Arm
Cadence's industry-first eUSB2V2 IP, built on the advanced TSMC N3P process and compliant with the latest embedded USB2 Version 2 standard, transforms computing devices by delivering unprecedented capabilities for laptops, AI video devices, and advanced image signal processor (ISP) systems.
When developing system-on-chip (SoC) solutions, the key features often minimize size, maximize performance, and achieve low power consumption while decreasing costs. These requirements are true for most industries, including AI-powered consumer devices, energy-intensive data centers, cloud-based enterprise systems, and smart autonomous vehicles.
Vinod Khera, Cadence
In this paper, we discuss the Transaction Level Model which is being developed to act as Virtual Prototype in digital image processors designed to fit into mobile applications. As part of our developments new methodology TLMdevice is also defined which provides way to connect TLM simulations to communicate with not only virtual host devices such as Graphical window, Keyboards but also real host devices like UART, Display and Sensors, so that data can be easily sent and received to/from during TLM simulation run
