Vendor: SmartDV Technologies Category: GDDR

GDDR7 DFI Verification IP

GDDR7 DFI Verification IP provides an smart way to verify the GDDR7 DFI component of a SOC or a ASIC.

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Verification IP Controller View all specifications

Overview

GDDR7 DFI Verification IP provides an smart way to verify the GDDR7 DFI component of a SOC or a ASIC. The SmartDV's GDDR7 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.

GDDR7 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR7 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Compliant with DFI version 4.0 or 5.0 Specifications.
  • Supports GDDR7 devices compliant with GDDR7 SGRAM draft specification.
  • Supports all Interface Groups.
  • Supports Write Transactions with Data mask.
  • Supports DRAM Clock disabling feature.
  • Supports Data bit enable/disable feature.
  • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
  • Supports frequency change protocol.
  • Supports Low power control features.
  • Supports Error signaling.
  • Supports DFI Read/Write Chip Select.
  • Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat, tphy_wrdata, trd_dataen and tphy_rdlat delays.
  • Constantly monitors DFI behavior during simulation.
  • Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.
  • Bus-accurate timing for min, max and typical values.
  • Notifies the test bench of significant events such as transactions, warnings.
  • Built in functional coverage analysis.
  • Supports callbacks, so that user can access the data observed by monitor.

Block Diagram

GDDR7 DFI VIP block diagram

Benefits

  • Faster test bench development and more complete verification of GDDR7 DFI designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the GDDR7 DFI testcases.
  • Complete UVM/OVM sequence library for GDDR7 DFI controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all classes, tasks and functions used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
GDDR7 DFI VIP
Vendor
SmartDV Technologies
Type
Verification IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about GDDR Interface IP

What is GDDR7 DFI Verification IP?

GDDR7 DFI Verification IP is a GDDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this GDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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