Vendor: SmartDV Technologies Category: GDDR

GDDR5 Synthesizable Transactor

GDDR5 Synthesizable Transactor provides a smart way to verify the GDDR5 component of a SOC or a ASIC in Emulator or FPGA platform.

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Overview

GDDR5 Synthesizable Transactor provides a smart way to verify the GDDR5 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's GDDR5 Synthesizable Transactor is fully compliant with standard JESD212C Specification and provides the following features.

Key features

  • Supports 100% of GDDR5 protocol standard JESD212C
  • Supports all the GDDR5 commands as per the specs
  • Supports all types of timing and protocol violation detection
  • Supports up to 8GB device density
  • Supports following device modes:
    • X16
    • X32
  • Supports all mode registers programming
  • Checks for following:
    • Check-points include power on, initialization and power off rules
    • State based rules, active command rules
    • Read/write command rules etc
    • All timing violations
  • Supports single ended interface for command, address and data
  • Supports double data rate (DDR) data (WCK)
  • Supports single data rate (SDR) command (CK)
  • Supports double data rate (DDR) addressing (CK)
  • Supports programmable burst length: 8
  • Supports programmable read latency and write latency
  • Supports write data mask function via address bus
  • Supports data bus inversion (DBI) & address bus inversion (ABI)
  • Supports input/output PLL/DLL
  • Supports address training
  • Supports cyclic redundancy check (CRC-8)
  • Supports programmable CRC read latency, write latency
  • Supports low power modes
  • Supports auto & self refresh modes
  • Supports auto precharge option for each burst access
  • Supports on-die termination (ODT) for all high-speed inputs
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

GDDR5 Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the GDDR5 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
GDDR5 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force one-size-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about GDDR Interface IP

What is GDDR5 Synthesizable Transactor?

GDDR5 Synthesizable Transactor is a GDDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this GDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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