Wideband Digital Down Converter (Digital DDC)
Overview
The IPrium-Wideband-DDC IP core is full-featured wideband digital downconverter and includes complex digital mixer and digital decimation filter with signal gain and phase correction.
Key Features
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
- Fully verified and real-time tested on a FPGA based development platform
- Considerations for easy ASIC integration
- Validated on IPrium Evaluation Boards
Deliverables
- VQM/NGC/EDIF netlists for Altera Quartus II, Xilinx ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
- IP Core testbench scripts
- Design examples for Altera, Xilinx, Lattice, and Microsemi (Actel) evaluation boards
- Free 1 year warranty and support period
Technical Specifications
Maturity
Silicon proven
Availability
Now
Related IPs
- 4-bit, 10 GSPS Analog to Digital Converter IP block
- 4-bit, 20 GSPS Analog to Digital Converter IP block
- ST 6-bit, 10 GSPS Analog to Digital Converter IP block
- 6-bit, 12 GSPS Analog to Digital Converter IP block
- ST 6-bit, 20 GSPS Analog to Digital Converter IP block
- 8-bit, 40 GSPS Analog to Digital Converter IP block