SMIC 55nm LL LPDDR interface for DRAM application

Key Features

• LPDDR interface for DRAM application;
• SMIC 55nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
• Cell Size (Width * height) 35um * 174um with DUP stagger bonding pads;
• Work voltage: 1.8V;
• Programmable drive-strength, Schmitt?trigger?enable input,optional pullup,pulldown resistor; support data rate up to 400Mbps;
• Suitable for 7, 8, 9 and 10 layers application ;

Technical Specifications