MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
Overview
The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of TSMC 40nm LP process.
Key Features
- Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface.
- - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016.
- - MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015.
- - MIPI alliance Specification for Camera Serial Interface 2 (CSI-2) Version 2.0 7 Dec 2016.
- Technology is TSMC 40nm LP 1p6M (4x1z) .
- Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 0.72Gbps at High-speed mode.
Block Diagram
Technical Specifications
TSMC
Pre-Silicon:
40nm
LP
Related IPs
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables
- MIPI D-PHY Rx ONLY v1.1 @1.5ghz Ultra Low Power & Low Area for IoT & Wearables
- MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)