MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
Overview
The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of TSMC 40nm LP process.
Key Features
- Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface.
- - MIPI alliance Specification for D-PHY Version 2.1 15 December 2016.
- - MIPI alliance Specification for Display Serial Interface (DSI) Version 1.3.1 Aug 2015.
- - MIPI alliance Specification for Camera Serial Interface 2 (CSI-2) Version 2.0 7 Dec 2016.
- Technology is TSMC 40nm LP 1p6M (4x1z) .
- Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 0.72Gbps at High-speed mode.
Block Diagram
Technical Specifications
Short description
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
Vendor
Vendor Name
TSMC
Pre-Silicon:
40nm
LP
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- MIPI D-PHY IP
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- TSMC 40nm LP combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode
- MIPI D-PHY