AVCI (Advanced VCI) Verification IP

Overview

AVCI (Advanced VCI) Verification IP provides an smart way to verify the AVCI (Advanced VCI) component of a SOC or a ASIC. The SmartDV's AVCI (Advanced VCI) Verification IP is fully compliant with standard AVCI (Advanced VCI) Specification and provides the following features.

AVCI (Advanced VCI) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AVCI (Advanced VCI) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant to AVCI (Advanced VCI) Protocol version 2.0
Support for all types of AMBA APB devices

Master
Slave

Support for programmable wait states, Split completion
Supports generation of out of order transcations
Configurable transfer size for read and write transactions
Flexibility to send completely configured data
Ability to inject errors during data transfer
On-the-fly protocol and data checking

Benefits

Faster testbench development and more complete verification of AVCI (Advanced VCI) designs.
Easy to use command interface simplifies testbench control and configuration of master and slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the AVCI (Advanced VCI) testcases.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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