16-Bit Sigma-Delta Stereo Audio CODEC with Microphone and Headphone, Fujitsu 65nm

Overview

The AR34F5B specifies a very low power stereo audio CODEC IP for multimedia audio system. The IP employs multibit sigma delta architecture. It includes built-in bandgap reference and on-chip regulators for better noise immunity. The IP is fabricated in Fujitsu 65nm process and can be ported to other 65nm or 55nm processes.

Key Features

16-bit Data Conversion
3.3V Analog Power Supply, 1.2V Digital Power Supply
SNR (DAC) > 89dB, SNR (ADC) > 85dB
Sampling Frequency: 8KHz~48KHz, can also operates up to 192KHz
Stereo Audio Recording for Microphone and 6 Line-In Channels
Stereo Audio Playback for Line-Out and/or Headphone
Automatic Level Control
Microphone 0/+20dB Pre-Amp and Microphone Current Bias to External EMC
Wide-Range PGAs with 0.5dB/Step Tuning Range
Pop/Click Noise Suppression
I2S Digital Audio Interface
I2C, SPI, MCU Controlling Interface
Very Low Power Consumption (NDA Required)
Ultra Small Core Area (NDA Required)

Benefits

The AR34F5B is a silicon-proven, easy-implementation audio CODEC IP. Its low power design is suitable for portable multimedia devices such as IPTV. SOC companies can take advantage in this proven IP to expedite their product development and reduce the time-to-market. Please contact us for more details.

Deliverables

Full Datasheet
Application Note
Integration Guidance
Behavior Model
GDSII Abstract (.LEF Format)
Timing Library (.LIB Format)
LVS Netlist (SPICE Compatible)
Physical Design Database (GDSII Format)
Silicon Validation Report
AE Support

Technical Specifications

Foundry, Node

Fujitsu 65nm, 55nm

Maturity

Silicon Proven

Availability

NOW

Request Info