100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process

Overview

100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process

Technical Specifications

Short description
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process
Vendor
Vendor Name
Foundry, Node
UMC 0.13um
UMC
Pre-Silicon: 130nm
×
Semiconductor IP