1.25G - 12.5G SERDES
Key Features
- Universal SERDES IP range from 1.25 – 10 Gbit/s
- Half data rate and quadrant data rate support
- 40-bit parallel data bus
- Independent channel power down
- Programmable transmit amplitude and TAP configurable FFE in transmitter
- Build in self test with multiple pattern generation and checking for production test
- Integrated on-die termination resistors
- Receiver detection support
- OOB signal generation and detection support
- Spread Spectrum clock generation (optional) and receive support
- Flexible reference clock frequency, 25 – 156.25 MHz
- Support 1, 2, 4 lanes
- No external component
- ESD: HBM/MM/CDM/Latch Up 2 kV/200 V/500 V/100 mA
Block Diagram
Technical Specifications
Short description
1.25G - 12.5G SERDES
Vendor
Vendor Name
Related IPs
- 0.6G - 12.5G Universal SerDes
- 12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 40LL
- 12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++
- 12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
- 12.5G Multiprotocol Serdes IP, Silicon Proven in TSMC 28HPC+
- Low Jitter Digital PLL – 1.25G/2.5G/5G