Overview
A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, and associated ESD. Also features an LDO optimized for use with 3.3V GPIO.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V refer ence which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
Operating Conditions
| Parameter |
Value |
| VDDIO |
1.8 or 3.3V |
| Core VDD |
0.8V |
| Tempeature |
-40C to 125C |
| Max Load |
50 pF |
Library Summary
| Item |
Description |
| 1.8V Cell size |
23um ×60um |
| 3.3V Cell size |
30um ×85um |
| I/O device |
1.8V Gate Oxide |
| BEOL |
13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB |
| Supply/ESD |
1.8 - 3.3V;0.9V; GND |
| GPIO |
see GPIO Features |
| GPI |
Fail safe input |
| Power |
Core and IO power. |
| Vref |
LDO optimized for GPIO |
| Analog |
Analog I/O with ESD |
| Proton Test |
64MeV, fluence 5E+11 (ESD only) |
Learn more about LDO Voltage Regulator IP core
Power management of battery-powered electronic devices is becoming increasingly more important for the microelectronics industry. This white paper details the difference between low dropout (LDO) voltage regulators that use external output capacitors and those that do not, and how your system designs can benefit from not using an output capacitor. Well-designed capless LDO voltage regulators can have multiple benefits, and they are presented here.
There are many factors that must be considered when developing a custom System on a Chip (SoC) for Internet of Things (IoT) applications. Chief among these are the power management circuits on the die. Vidatronic offers this white paper to discuss these considerations and all of the various circuit blocks that can be found in this application. Vidatronic IP solutions are discussed and the benefits they bring to IoT SoC designers.
Power management poses challenges
Power management of battery-powered electronic devices is becoming increasingly more important for the present and future microelectronics industry. This application note details the difference between low dropout (LDO) voltage regulators that use output capacitance and those that do not and how your system designs can benefit from or be improved by not using an output capacitor.
The vast array of on-chip LDO options and characteristics can make the selection process complex.
Linear voltage regulators are key components in any power-management system that requires a stable and ripple-free power supply. A subset of linear voltage regulators is a class of circuits known as low dropout (LDO) regulators. This paper explains the fundamentals of LDOs and introduces Vidatronic’s LDO technology which solves many of the known shortcomings of LDO circuits.
