CDM Dependence on Device Capacitance
This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.
Vendor:
Certus Semiconductor
Category:
LDO Voltage Regulator
1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, a…
Overview
A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, and associated ESD. Also features an LDO optimized for use with 3.3V GPIO.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V refer ence which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
Operating Conditions
| Parameter | Value |
| VDDIO | 1.8 or 3.3V |
| Core VDD | 0.8V |
| Tempeature | -40C to 125C |
| Max Load | 50 pF |
Library Summary
| Item | Description |
| 1.8V Cell size | 23um ×60um |
| 3.3V Cell size | 30um ×85um |
| I/O device | 1.8V Gate Oxide |
| BEOL | 13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB |
| Supply/ESD | 1.8 - 3.3V;0.9V; GND |
| GPIO | see GPIO Features |
| GPI | Fail safe input |
| Power | Core and IO power. |
| Vref | LDO optimized for GPIO |
| Analog | Analog I/O with ESD |
| Proton Test | 64MeV, fluence 5E+11 (ESD only) |
Key features
- 2mA, 4mA, 8mA and 16mA drive strengths
- Pairs with optimized LDO (3.3V only)
- Full-speed output enable
- Independent power sequencing
- Integrated power-on-control circuitry
- Selectable Schmitt trigger receiver
- 50K ohm selectable pull-up or pull-down resistor item ESD: 2KV HBM, 500V CDM3, 2KV IEC 61000-4-24
- Standards
- 1.8V and 3.3V LVCMOS
- 1.8V and 3.3V LVTTL
- I2C and SPI (Input only)
Block Diagram
Certus_GF12 block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 12nm | LP | — |
Specifications
Identity
Part Number
Certus_GF12
Vendor
Certus Semiconductor
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United States
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Frequently asked questions about LDO Voltage Regulator IP cores
What is 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm?
1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm is a LDO Voltage Regulator IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for globalfoundries.
How should engineers evaluate this LDO Voltage Regulator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LDO Voltage Regulator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.