Yawn... New EDA Leader Results Are Coming
We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.
Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce. I still have my brass-plated letter opener which Cadence gave to every employee in September 1990 when Cadence moved to the NYSE. Heck I even was excited to see the SVR (Silicon Valley Research, aka Silvar-Lisco) announcements. It was exciting to follow the industry then.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- ICCAD Keynote: Design of Secure Systems - Where are the EDA Tools?
- CES 2020: The robots are coming...
- Silicon IP to take over CAE in EDAC results... soon but not yet!
- Silicon IP has taken over CAE in EDAC results... showing how bad have been analyst in forecasting the IP market!
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power