Yawn... New EDA Leader Results Are Coming
January 21, 2013
We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.
Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce. I still have my brass-plated letter opener which Cadence gave to every employee in September 1990 when Cadence moved to the NYSE. Heck I even was excited to see the SVR (Silicon Valley Research, aka Silvar-Lisco) announcements. It was exciting to follow the industry then.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related Blogs
- ICCAD Keynote: Design of Secure Systems - Where are the EDA Tools?
- CES 2020: The robots are coming...
- Silicon IP to take over CAE in EDAC results... soon but not yet!
- Silicon IP has taken over CAE in EDAC results... showing how bad have been analyst in forecasting the IP market!
Latest Blogs
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design