The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…
- Single-Protocol PHY
The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…
FPGA Proven PCIe Gen6 Controller IP
Deployed in Tier 1 Leaders.
Our latest PCIe gen 6 controller IP, which is "NoC aware", provides a high-speed interface for efficient data transfer and system…
PCIE Gen6 digital controller (Dual Mode)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
PCIE Gen6 digital controller (Root Complex)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
PCIE Gen6 digital controller (End Point)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
PCIe 6.0 (Gen6) Premium Controller
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
The PCI Express® (PCIe®) Controller IP is a configurable, performance-optimized core designed for ASIC and FPGA integration.
Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
Used by all PCIe, IP, and SoC design verification teams for all generations.The Cadence® Verification IP (VIP) for PCI Express® (…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
The PCIe Switch Verification IP provides an effective & efficient way to verify the components interfacing with the PCIe Switch i…
The NVMe 2.2 Verification IP provides an effective & efficient way to verify the components interfacing with the PCIe/AXI interfa…
The NVMe 2 Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
PCIe 6.0 / CXL 3.0 PHY & Controller
The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and …