MRAM Memory Model provides an smart way to verify the MRAM component of a SOC or a ASIC.
- MRAM / RRAM
MRAM Memory Model provides an smart way to verify the MRAM component of a SOC or a ASIC.
MRAM Synthesizable Transactor provides a smart way to verify the MRAM component of a SOC or a ASIC in Emulator or FPGA platform.
Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all s…
Hierarchical scalability is the foundation principle of the Fibonacci machine-learning (ML) system-on-chip (SoC).
Fully synthesizable and configurable memory subsystem IP that enables significant improvement in power, performance and endurance…
DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
The DDR (Double Data Rate) controller IP is for LPDDR4 and DDR4/3/3L optimized for low latency.
, patented memory technology based on industry proven MRAM.
Slave side SPI/QPI controller 133MHZ
This SPI/QPI PHY IP is fully compatible with Macronix NOR Flash SPI products.