1-VIA
•
HQ:
UK
1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wid…
- Multi-Protocol PHY
Compare 856 Half-Power SERDES IP Listing from 74 vendors
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Nano Silicon• HQ: Australia
IP
- Multi-Protocol PHY
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Silicon Creations• HQ: USA
Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and prove…
- TSMC
- 40nm
- LP
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SerDes Hard Macro-IP in GlobalFoundries 22FDX
Global IP Core Sales• HQ: GermanyThe SerDes Hard Macro-IP in GlobalFoundries 22FDX is an Off-the-Shelf IP.
- GlobalFoundries
- 22nm
- FDX
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Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 28nm
- HPC
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Programmable Low Power SERDES Receiver on TSMC CLN65LP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 65nm
- LP
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Programmable Low Power SERDES on TSMC CLN40G
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 40nm
- G
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Programmable Low Power SERDES on TSMC CLN28HPL
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 28nm
- HPL
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PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- TSMC
- 5nm
- N5A
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PCI Express Gen5 SERDES PHY on Samsung 8LPP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- Samsung
- 8nm
- 8LPP
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PCI Express Gen4 SERDES PHY on Samsung 7LPP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- Samsung
- 7nm
- SF7LPP
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PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- TSMC
- 5nm
- N5
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PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- Samsung
- 8nm
- 8LPP
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PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- Samsung
- 8nm
- 8LPP
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PCI Express Gen3 SERDES PHY on TSMC CLN40G
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- TSMC
- 40nm
- G
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PCI Express Gen3 SERDES PHY on Samsung 7LPP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- Samsung
- 7nm
- SF7LPP
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PCI Express Gen3 SERDES PHY on Samsung 28LPP
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- Samsung
- 8nm
- 8LPP
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PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- Samsung
- 28nm
- FDS
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Custom Programmable Low Power SERDES on GLOBALFOUNDRIES 65G
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
- GlobalFoundries
- 65nm
- G
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Innosilicon Technology Ltd• HQ: China
The 32G SerDes PHY is a configurable IP solution capable of supporting data rates of up to 32 Gbps per lane.
- Multi-Protocol PHY