Linear Regulator IP, Output: 3.3V/100mA, UMC 0.15um SP process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.15um SP Logic process.
- UMC
- 150nm
- SP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Linear Regulator IP, Output: 3.3V/100mA, UMC 0.15um SP process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.15um SP Logic process.
Two Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous Single Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous high density Single Port SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec.
ROM Compiler IP, UMC 0.15um SP process
UMC 0.15um SP Logic process synchronous VIA2 programmed ROM memory compiler.
D/A Converter IP, 16 bits, 96Ksps, UMC 0.18um G2 process
16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.18um GII Logic process.
10-Bit 44MSPS dual channel differential current output Digital-to-Analog converter, UMC 0.18um GII Logic process.
Standard Cell (Generic) Library IP, 8 tracks, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density Core Cell Library.
Specialty PCI IO IP, UMC 0.15um SP process
UMC 0.15um SP process true 3.3V PCI IO cells.
Specialty OSC IO IP, UMC 0.15um SP process
UMC 0.15um SP process true 1.5V Oscillator IO cells.
Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.15um SP process
UMC 0.15um SP process standard Multi-Voltage IO.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.15um SP process
UMC 0.15um SP Logic process standard Core Cell Library.
Specialty PCI IO IP, 5V tolerance, UMC 0.15um SP process
UMC 0.15um SP process 5.0V tolerant PCI 33/66 IO cells.
Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process
UMC 0.18um LL Logic process standard Multi-Voltage IO.
Specialty SSTL IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 2.5V SSTL2 IO cells.
Specialty PCI IO IP, 5V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 5.0V tolerant PCI IO cells.