Single Port SRAM Compiler IP, UMC 0.11um EEPROM process
UMC 0.11um EE2PROM/LL 1.5V high density Single Port SRAM compiler.
- UMC
- 110nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Single Port SRAM Compiler IP, UMC 0.11um EEPROM process
UMC 0.11um EE2PROM/LL 1.5V high density Single Port SRAM compiler.
Single Port SRAM Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE Logic process Synchronous Single Port SRAM memory compiler with 1.41um2-Bit cell.
Single Port SRAM Compiler IP, UMC 0.11um LL process
UMC 0.11um AE/LL eFlash Single Port SRAM.
Single Port SRAM Compiler IP, UMC 0.11um LL/AE process
UMC 0.11um LL/AE (AL Enhancement) Logic process Single Port SRAM compiler with 141-Bit cell.
Single Port SRAM Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process 1.41um2 Cell Single Port SRAM compiler.
Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Dual Port SRAM with redundancy feature.
Dual Port SRAM Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Dual Port SRAM memory compiler.
Dual Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process
UMC 40nm Logic process synchronous high density Dual Port SRAM memory compiler with redundancy.
Dual Port SRAM Compiler IP, UMC 0.18um eFlash/G2 process
UMC 0.18um eFlash GII Logic process high density Dual Port SRAM compiler.
Two Port Register File Compiler IP, UMC 0.11um SP/AE process
UMC 0.11um SP/AE (AL Advance Enhancement) Logic process synchronous Two Port SRAM memory compiler.
Dual Port SRAM Compiler IP, Output: 1.8432MHz, UMC 40nm LP process
UMC 40nm LP Logic process synchronous high density Dual Port SRAM memory compiler.
USB 2.0 OTG PHY IP, UMC 55nm LP process
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 55nm LP Low-K Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 0.11um HS/AE process
USB1.1 PHY feature USB 1.1 On-The-Go PHY, UMC 0.11um HS/AE (AL Enhancement) Logic process.
USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 0.11um HS/AE process
Crystal-Less USB2.0 PHY, UMC 0.11um HS/AE (AL Enhancement) Logic process.
USB 1.1 PHY IP, UMC 0.13um LL/FSG process
USB 1.1 transceiver, UMC 0.13um LL Logic/FSG process.
SATA III PHY IP, Gen-3, UMC 55nm SP process
Serial ATA I, II, III PHY, UMC 55nm SP/RVT Low-K Logic process.
SATA III PHY IP, Gen-3, UMC 0.11um HS/FSG process
6G/3G/1.5G Serial ATA PHY, UMC 0.11um HS/FSG Logic process.
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process.
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 55nm SP process
MIPI Transmitter 80~1500MHz, UMC 55nm SP/RVT Low-K Logic process.
MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 55nm SP process
MIPI Receiver 80~1500MHz, UMC 55nm SP/RVT Low-K Logic process.