Specialty DDR IO IP, DDR2/DDR1/MDDR, UMC 0.11um HS/AE process
UMC 0.11um AE/HS Logic process DD1/DDR2 combo MDDR IO Cell Library.
- UMC
- 110nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Specialty DDR IO IP, DDR2/DDR1/MDDR, UMC 0.11um HS/AE process
UMC 0.11um AE/HS Logic process DD1/DDR2 combo MDDR IO Cell Library.
General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 55nm eFlash process
UMC 55 nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate process 1.8V/2.5V/3.3V Multi-Voltage BOAC IO Cell Library.
General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 1.8V/2.5V/3.3V Multi-Voltage BOAC IO Cell Library.
UMC 40nm LP/RVT Logic process 5V Tolerance Generic POC IO with BOAC solution.
General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 1.8V BOAC IO Cell Library (with customized PU/PD function).
General Purpose IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Logic process true 1.0/3.3V standard IO Cell Library (3.3V Generic IO).
General Purpose IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Logic process true 1.0/3.3V standard IO Cell Library (3.3V Analog IO).
General Purpose IO IP, True 3.3V, UMC 90nm SP process
UMC 90nm SP/RVT process true 3.3V standard IO Cell Library Using 3.3V GOX52 IO.
General Purpose IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Logic process TRUE 2.5V Generic IO Library.
General Purpose IO IP, 3.3V tolerance, UMC 90nm SP process
UMC 90nm SP/RVT process 3.3V tolerant IO Cell Library.
General Purpose IO IP, UMC 90nm SP process
UMC 90nm Low-K SP process true 2.5V standard IO Cell Library.
General Purpose IO IP, 3.3V tolerance, UMC 90nm SP process
UMC 90nm Low-K SP process 3.3V tolerant IO Cell Library.
General Purpose IO IP, UMC 90nm SP process
UMC 90nm SP/RVT Low-K Logic process True 3.3V Generic IO Cell Library.
General Purpose IO IP, UMC 90nm Logic process
UMC 90nm 2.5V over-drive 3.3V GOX52 process IO.
General Purpose IO IP, UMC 90nm LL process
UMC 90nm LL Logic/RVT process true 1.2/3.3V standard IO Cell Library (3.3V Generic IO).
General Purpose IO IP, UMC 90nm LL process
UMC 90nm LL/RVT process true 3.3V standard IO Cell Library Using 3.3V GOX52 IO.
General Purpose IO IP, UMC 90nm LL process
UMC 90nm LL/RVT process true 2.5V standard IO Cell Library.
General Purpose IO IP, UMC 90nm LL process
UMC 90nm LL Logic/RVT process 2.5V standard IO Cell Library (MDDR IO).
General Purpose IO IP, 3.3V tolerance, UMC 90nm LL process
UMC 90nm LL/RVT process 3.3V tolerant IO Cell Library.
General Purpose IO IP, UMC 90nm LL process
UMC 90nm LL/RVT process true 3.3V standard IO Cell Library Using 3.3V GOX52 IO.